IP Cores

What Are IP Cores All About?

• “IP” in this sense means “intellectual property”

Which really means “circuit designs” cleaned up and made available to other engineers

What’s a Hard Core?

A packaged chip with the plastic package removed

Shape is fixed, electrical characteristics are fixed, size is fixed, functions are fixed, silicon process (e.g., 0.25-micron CMOS) is fixed – everything is fixed!

GDSII (Hard version) is just another view

  • Provided to expedite other designs on some process

  • porting is done via re-synthesis

  • full custom sections ported by porting tools or manually

What’s a Soft Core?

The same circuit design delivered in “source code” format instead of physical film or physical-layout information

Not as flexible as you might think!

Electrical characteristics are fixed, functions are fixed – everything but size and shape!

Equivalent to delivering C source code. The program doesn’t change at all, only the details of the executable binary you create

• “Synthesizable” and “soft” do not mean changeable

All Digital IP starts as soft IP

  • RTL model is reference implementation model

  • specification can be written and/ or executable (C++ or behavioral HDL)

  • synthesizable RTL used to generate all hard views

  • Full custom block can be used to replace blocks in critical path

What’s a Configurable Core?

Starts with a soft (synthesizable) core

Gives you the ability to alter or modify the “source code” of the hardware and still make working hardware

This is both a technical feature and a legal detail

Like changing Grandma’s cookie recipe to add chocolate chips

The scope of your changes is usually somewhat limited to avoid hardware bugs and to ease testing